1. Field of the Invention
The present invention relates to a semiconductor device and a method for forming the same. Particularly, it is applicable to a liquid crystal electro-optical device or a full contacted image sensor device etc.
2. Description of the Prior Art
So far, the insulated gate field effect semiconductor device has been well known and widely used in various fields. This semiconductor device is formed on a silicon substrate and is utilized as IC or LSI, integrating many semiconductor elements functionally.
On the other hand, a thin film type insulated gate field effect semiconductor device (hereinafter to be referred to as TFT) which is formed by laminating thin films on an insulating substrate has started to be positively used in such parts as a switching element, a driving circuit for a picture element of the liquid crystal electro-optical device, and a reading circuit part of a full contacted image sensor.
As mentioned above, the TFT is formed by laminating thin films on the insulating substrate, using gaseous phase method. The temperature of the forming-atmosphere is such low as around 500xc2x0 C. even at the highest. Then, it is possible to use cheap soda glass or borosilicate glass etc. as a substrate. Therefore, TFT has such merits as it can be formed on a cheap substrate, its maximum size is limited to only the apparatus size applied to the thin film forming by the gaseous phase method, and it is easy to form a transistor on a large area substrate. Then, it has been expected and also partly realized that the TFT will be applied to a liquid crystal electro-optical device in a matrix structure having a lot of picture elements, and a one-dimensional or two-dimensional image sensor.
FIG. 2 is a schematic diagram showing a typical structure of the conventional TFT, in which reference numeral 1 designates an insulation substrate made of glass, 2 an amorphous thin film semiconductor, and a reference numeral 3 designates a source and a drain region, a reference numeral 7 designates a source and a drain electrode, and a reference numeral 8 designates a gate electrode.
Such TFT is generally prepared as follows. At first, a semiconductor film will be formed on the substrate, and a semiconductor region 2 will be formed into an island shape at a necessary part, by patterning the semiconductor film using the first mask. Then, the gate insulation film material will be formed and the gate electrode material will be formed thereon, and the gate insulation film material and the gate electrode material will be patterned using the second mask to form the gate insulation film 6 and the gate electrode 8.
After that, the source and drain regions 3 will be formed by a self-alignment in the semiconductor region 2, using the mask of photoresist formed with the third mask and the gate electrode 8 as a mask. Then, an interlayer insulating film 4 will be formed. Contact holes will be formed in the interlayer insulating film using the fourth mask, to connect electrodes to the source and drain regions 3. Finally, the electrode 7 will be formed to complete the preparation of TFT, by patterning the electrode material which was previously formed, using the fifth mask.
As described above, it has been needed for the preparation of usual TFT to use five sheets of mask, especially six sheets of mask in case of complementary type TFTs. As a matter of course, the more IC is complicated, the more sheets of mask will be needed. In this way, using many masks requires an intricated process in the preparation of TFT element, and increases inevitably the number of mask alignments, the result being in that it brings about the falling down of yield and productivity of the TFT element preparation. Further, it poses a problem that the large-sizing of an electronic device using the TFT element, and the small-sizing of TFT element itself, and the fine patterning render the above yield and productivity more fall down.
Accordingly, it is an object of the present invention to provide a novel structure of the insulated gate field effect semiconductor device which can decrease the number of masks needed for the preparation of TFT.
It is another object of the present invention to provide a process which does not need the complicated one for the preparation of TFT.
The present invention, therefore, is concerned with the novel structure of the insulated gate field effect semiconductor device, and with the simple preparation process therefor, which is capable of preparing the TFT with less number of masks compared with the conventional process.
That is, the present invention provides an insulated gate field effect semiconductor device comprising:
an anodic oxidation film being laid around the side of a gate electrode of a TFT, said anodic oxidation film comprising a material of said gate electrode; and
electrodes being in contact with the upper surfaces and the sides of source and drain regions, said electrodes being extended covering the upper surface of an insulation film (the anodic oxidation film) laid around the side of said gate electrode.
As shown in FIG. 1 which is a schematic cross-sectional view of the TFT, according to the present invention, the anodic oxidation film 10 is laid at least around the side of the gate electrode 8, The upper and the side surfaces of the source and drain regions 3 protrude a little from the verge surface of the anodic oxidation film. (A total width of the anodic oxidation film and the gate electrode is smaller than width of a semiconductor layer comprising the source and drain regions 3 and a channel 2 in FIG. 1. Also, width of the gate insulating layer of the TFT is smaller than the width of the semiconductor layer.) At this protruded area, the electrodes 7 are connected to the source and drain regions, and it takes a large connective area. Further, the electrode 7 extends to the upper part of the insulation film 11 on the gate electrode 8. At this part, it is patterned and is separated into each electrode.
FIG. 3 indicates a schematic process for the preparation of TFT structure shown in FIG. 1. The diagrams in the specification of the present invention show only outlines for the explanation, and these are a little different from the actual ones in their sizes and shapes. Hereafter, one example of the TFT preparation process of the present invention will be explained in accordance with FIG. 3.
First of all, a semiconductor layer 2 will be formed on a glass substrate 1, e.g., a crystallized glass having a heat resisting properties, as indicated in FIG. 3(A). As the silicon semiconductor layer, such wide kinds of semiconductor as amorphous, or polycrystal semiconductor are used. As a forming method, it may be selected to use plasma-CVD, sputtering, or heat-CVD method, according to the kind of semiconductor employed. For example, a polycrystal silicon semiconductor is used in the following explanation.
Next, silicon oxide film 6 to be a gate insulating film will be formed on the semiconductor 2, and then a gate electrode material, here used aluminum, will be formed on the silicon oxide 6. Upon this, a silicon oxide film as the insulation film 11 will be formed by sputtering method. After that, the insulation film 11 and the gate electrode 8 will be patterned, using the first mask {circle around (1)}. After that, non porous aluminum oxide 10 will be formed at least around the side of the gate electrode nearby a channel region as shown in FIG. 3(B), by effecting an anodic oxidation around the side area of the electrode 8, in an electrolytic solution for the anodic oxidation.
As the solution for the anodic oxidation, typically, such a strong acid solution as sulfuric, nitric, and phosphoric acid, or a mixed acid solution of such organic acid as tartaric, and citric acid with such organic solvent as ethylene glycol, and propylene glycol can be utilized. Also if necessary, it is possible to mix a salt or an alkali in the solution, in order to adjust the PH of the solution.
A propylene glycol will be added to 3% by weight solution of tartaric acid, in the ratio of 9 parts of propylene glycol per 1 part of the solution, to prepare AGW electrolytic solution, in which this substrate will be immersed. An aluminum gate electrode will be connected to an anode of electric source, and D.C. power will be applied using a platinum as a cathode.
The anodic oxidation condition is as follows. At first, under constant current mode, 2.5 mA/cm2 of an electric current density will be passed for 30 min. After that, under constant voltage mode, it will be treated for 5 min. to form aluminum oxide in 2500 xc3x85 thick around the side of gate electrode. The insulation properties of the aluminum oxide film will be measured, using the aluminum oxide sample obtained by the same oxidation treatment with the above forming. It is an aluminum oxide film having 109 xcexa9m of resistivity and 2xc3x97105 V/cm of dielectric strength.
Also in the observation of the sample surface with a scanning electron microscope, the uneveness of the surface can be come into view, by enlarging the surface to about 8000 magnifications. But the very small hole can not be noticed, which is a certain evidence of a good insulation film.
Next, on this upper surface, a silicon oxide film 12 will be formed by means of plasma-CVD method followed by an anisotropic etching treatment in the vertical direction to the substrate to remain the silicon oxide 13 at the side position of convex part which is composed of the insulation film 11, the gate electrode 8, and the anodic oxidation film 10, as illustrated in FIG. 3(D).
This silicon oxide film 12 will be formed at such low temperature as 200xc2x0 C., which is lower than the usual temperature of forming-atmosphere, so that the etching speed will be higher than that of insulation film 11. As this film, an organic resin film and the like can be used in addition to the silicon oxide film. Then, the under part of semiconductor layer 2 will be etched to remove it by self-alignment method, using the mask of the remained silicon oxide 13, and the convex part composed of the insulation film 11, the gate electrode 8, and the anodic oxidation film 10. This treating state is shown in FIG. 3(E), and the upper surface state is shown in FIG. 4(A) Also the cross-sectional view taken along line A-Axe2x80x2 of FIG. 4 is shown in FIG. 3.
Following this state, the silicon oxide 13 and the silicon oxide of a portion of the gate insulating film 6 will be removed by etching with the convex part as a mask to expose portions of the semiconductor layer 2 outside the side of the gate electrode as shown in FIG. 3(F) and FIG. 4(B). The impurity will be doped in the exposed portions to be source and drain regions. As indicated in FIG. 3(F), phosphorus ion will be treated to implant from the upper surface of substrate, using the mask of the anodic oxidation film 10 of the gate. In this way, the source and drain regions 3 will be formed. After that, the source and drain regions will be activated, treating with a laser annealing to irradiate a laser beam to it. As the activation treatment, heat-annealing and so on can be used, besides the above laser annealing.
Next, an aluminum to be source and drain electrodes will be formed on this upper surface. Then, the aluminum will be etched to effect the prescribed patterning by using the second mask {circle around (2)}, and will be split into both the source and drain electrodes, the state of which is indicated in FIG. 4(C). Lastly, the semiconductor layer 2 protruded around will be etched to remove it, using both the source and drain electrodes 7 and the convex part as a mask. Thus, the preparation of TFT will be completed, as shown in FIG. 3(G) and FIG. 4(D).
The preparation process of TFT described in the above is just one example, and the present invention is not limited to the above process. For example, although doping process of impurities to the source and drain regions is carried out after patterning the semiconductor layer 2 in the above description, as shown in FIG. 3(F), it is possible to implant impurity ions into source and drain regions in the condition shown in FIG. 3(B) with the insulation film 11 as a mask.
As the other example of preparing TFT shown in FIG. 1, a schematic diagram of the preparing process is indicated in FIG. 5. In the preparing process of TFT in FIG. 5 a conventional technology is applied without employing such specific technology as the anisotropic etching adopted in the preparing process of FIG. 3.
In the same way with the case of FIG. 3, after a silicon semiconductor film is formed on the whole area of an insulation substrate 1, the semiconductor island 2 corresponding to the part of TFT element including the source and drain regions and the channel region thereof will be formed, by patterning the semiconductor film using a first mask. The plan view at this time is shown in FIG. 6(A), and the cross-sectional view of around the source, drain, and gate of the TFT is shown in FIG. 5(A).
Next, the gate insulation film 6, the aluminum 8 of gate electrode, and the insulation film 11 will be sequentially formed as shown in FIG. 5(B), covering this upper surface. Then, these films will be etched to complete the convex part as shown in FIG. 5(C), by using a second mask, and the semiconductor film 2 will be exposed from the convex part, so that the gate part will be formed at the prescribed position of the semiconductor island 2. A plan view at this time is shown in FIG. 6(B).
Under this situation, the anodic oxidation film 10 will be formed nearby the side of the gate electrode 8 in the same process of FIG. 3(B), resulting in the state of FIG. 5(C). Next to this, the source and drain regions 3 will be formed by doping impurity ion for source and drain in the exposed semiconductor island 2, as shown in FIG. 5(D). The ion doping will be conducted by the following way. The doping direction is slantweise or the diffusional treatment of impurity will be effected, and the boundary between the source or drain and the channel region is located around the end of gate electrode 8, i.e., to the inner side of the end of anodic oxidation film 10, thereby making it possible to keep a sufficient insulating properties with only the anodic oxidation film 10, without any short circuit, even if the source and drain electrodes are provided nearby contact between the anodic oxidation film and the gate insulation film 6. Next, a metal film will be formed, covering all of these surfaces. After that, the metal film will be patterned using a third mask, enabling the source and drain electrodes 7 to be split and to be extended up to the insulation film 11 and to obtain the structure as shown in FIG. 5(E). Then, an etching will be effected using the source and drain electrodes 7 as masks, to get rid of the semiconductor film protruded from the electrodes 7, and thus the TFT of the present invention will be obtained, as shown in FIG. 6(C).
In comparison with the preparing method shown in FIG. 3, if the semiconductor layer is patterned into an island including a TFT region therein by using a photomask newly before the forming process of gate electrode after forming of the semiconductor layer 2, the substrate or the insulation film on the substrate will only exist under the lead wiring part of gate electrode, without the existence of semiconductor layer 2 as shown in FIG. 6. At this part, it is possible that the condenser will not constitute. This constitution makes it possible to prepare the TFT which is capable of higher response, using three sheets of mask. This situation is illustrated in FIG. 6(D) which is a fragmentary cross-sectional view of taken along line B-Bxe2x80x2 of FIG. 6(C).
As evident in the above, it is possible to prepare TFT using only two or three sheets of mask, in accordance with the present invention. It is also possible to prepare the complementary TFTs, adding more one or two sheets of mask. Further, the connection to the gate electrode from outside can be effected, by forming an anodic oxidation film so that a part of gate electrode is not contacted with an electrolytic solution for the anodic oxidation, in the treatment of anodic oxidation, or by selectively etching the source and drain electrodes or the anodic oxidation film to remove the anodic oxidation film exposed to the outside, after etching the last unnecessary semiconductor layer. Of course, it can be connected by making a hole suitable for the contact in a special place, using new other mask.